1. Field of the Invention
The present invention relates generally to integrated circuit technology and, more specifically, the present invention relates to compensated integrated circuit buffers.
2. Description of the Related Art
To achieve high performances in modern integrated circuits, it is often necessary to utilize high speed buffer circuits such as for example input/output buffers. Integrated circuits generally interface with the high speed busses with input/output buffers. As integrated circuit technology continue to advance, the frequencies at which the integrated circuits operate increase accordingly. It has been a considerable challenge for circuit designers to design busses that are able to match the speed performance of the core speed of modern central processing units (CPUs). One reason for the difficulty of continuously increasing bus speeds to match the continuously increasing CPU core speeds is that input/output buffers coupled to the busses must often operate across a wide variety of operating conditions. For instance, the performance of an input/output buffer changes with respect to conditions such as process, voltage and temperature.
The use of impedance compensated input/output buffers have provided one prior art solution to the problems associated with the changes in operating conditions such as process, voltage and temperature. Impedance compensated input/output buffers address the problems associated with varying conditions by providing mechanisms to help maintain the optimum characteristics of input/output buffer drivers over a wide range of operating conditions.
FIG. 1 is an illustration of a prior art impedance compensated input/output buffer 101 that employs digital impedance compensation, which relies basically on the same principles as an analog-to-digital converter. In this scheme, input/output buffer 101 includes compensation devices, which are shown as a plurality of transistors 107A-C coupled in parallel between an output pin 113 and ground. Compensation unit 121 generates digital information via signals 111A-C, which indicate the number of parallel coupled transistors 107A-C in every buffer that should be activated at a given time to compensate for varying operating conditions.
For example, under slow operating conditions, which include low voltage, high temperature and slow process corner, many transistors 107A-C may need to be activated to pole the voltage at the output pin 113 to ground. In contrast, under faster operating conditions, fewer parallel coupled transistors 107A-C may need to be switched on for similar performance.
Although prior art input/output buffer 101 has the ability to compensate for varying operating conditions, one limitation of input/output buffer 101 is that it is difficult to verify the proper functionality of compensation unit 121 and parallel coupled transistors 109A-C since the parallel coupled transistors 109A-C create logic redundancies. Specifically, transistors 109A-C are coupled and parallel between node 119 and ground. For optimum performance, it is desired that all transistors 109A-C are completely functional. There is the possibility that in a testing environment, one or more of the parallel coupled devices 109A-C may not function properly due to a defect, but the remaining devices could still function properly. A tester (not shown) coupled to output pin 113 and node 119 would be unable to detect a defective device based on logic levels or simple timing. As a consequence, the defective device may not be detected in a testing environment but could, however, cause input/output buffer 101 to fail in a system environment.
Another limitation of compensation unit 121 is that if it is desired to deliberately adjust the control signals 111A-C to adjust the characteristics of compensated input/output buffer 101, it is generally necessary to precisely adjust or vary the resistance of resistor R1 or reference voltage V.sub.REF 117. It is appreciated that the need to carefully and precisely adjust the resistance of resistor R1 or the value of reference voltage V.sub.REF 117 may be a relatively difficult and tedious task for an integrated circuit designer that desires to adjust the control signals 111A-C generated by compensation unit 121.
Therefore, what is desired is a method and an apparatus for controlling a compensated buffer. Such a method and apparatus would provide improved control of the compensation unit output signals without the need of precisely adjusting or varying the reference resistor or voltage values coupled to the compensation units. Such a method and apparatus would also provide enhanced observability of a compensation unit of a compensated buffer to facilitate the testing of the logic redundancies created by the parallel coupled nature of the devices of compensated input/output buffers.